cadenceIC5141可能大家用的比较多，因为在使用IC610时需要把工艺库的cdb格式转化为OA格式，当然使用该软件就不需要转了，使用很方便，其实很安装相对于对于IC610来说简单很多。下面就基本的安装总结如下：
工具/原料
PC
CADENCEIC5141
VMWARE
方法/步骤
1、下面是修改.bashrc评鲦易纪文件#.bashrc#Userspe艘早祓胂cificaliasesandfunctionsaliaslmli='/home/eda/ic5141/tools/bin/lmgrd-c/home/eda/ic5141/share/license/license.dat'aliasopenbook='CDS_ROOT/tools/dfII/bin/cdsdoc'#Sourceglobaldefinitionsif[-f/etc/bashrc];then./etc/bashrcfiexportCDS_ROOT=/home/eda/ic5141exportCDS_LIC_FILE=5280@localhostexportLM_LICENSE_FILE=$CDS_ROOT/share/license/license.datexportCDS_Netlisting_Mode=AnalogexportPATH=$CDS_ROOT/tools/spectre/bin:$CDS_ROOT/tools/bin:$CDS_ROOT/tools/dfII/bin:$PATH~
2、然后哦就lmli[redhat3@localhostredhat3]$l葡矩酉缸mliIncorrectlybuiltbi荏鱿胫协narywhichaccesseserrnoorh_errnodirectly.Needstobefixed.[redhat3@localhostredhat3]$16:19:05(lmgrd)-----------------------------------------------16:19:05(lmgrd)PleaseNote:16:19:05(lmgrd)16:19:05(lmgrd)Thislogisintendedfordebugpurposesonly.16:19:05(lmgrd)Therearemanydetailsinlicensingpolicies16:19:05(lmgrd)thatarenotreportedintheinformationlogged16:19:05(lmgrd)here,soifyouusethislogfileforanykind16:19:05(lmgrd)ofusagereportingyouwillgenerallyproduce16:19:05(lmgrd)incorrectresults.16:19:05(lmgrd)16:19:05(lmgrd)-----------------------------------------------16:19:05(lmgrd)16:19:05(lmgrd)16:19:05(lmgrd)FLEXlm(v8.4a)startedonlocalhost(linux)(2/2/2015)16:19:05(lmgrd)Copyright(c)1988-2003byMacrovisionCorporation.Allrightsreserved.16:19:05(lmgrd)USPatents5,390,297and5,671,412.16:19:05(lmgrd)WorldWideWeb:http://www.macrovision.com16:19:05(lmgrd)Licensefile(s):/home/eda/ic5141/share/license/license.dat16:19:05(lmgrd)lmgrdtcp-port528016:19:05(lmgrd)Startingvendordaemons...16:19:05(lmgrd)Startedcdslmd(internettcp_port32781pid26823)Incorrectlybuiltbinarywhichaccesseserrnoorh_errnodirectly.Needstobefixed.16:19:05(cdslmd)FLEXlmversion8.4a16:19:05(cdslmd)Serverstartedonlocalhostfor:10016:19:05(cdslmd)111114001214116:19:05(cdslmd)12500140001401016:19:05(cdslmd)14020140401410116:19:05(cdslmd)14111141201413016:19:05(cdslmd)141401441020016:19:05(cdslmd)20120201212012216:19:05(cdslmd)20123201242012716:19:05(cdslmd)20128202202022116:19:05(cdslmd)202222022720616:19:05(cdslmd)207210602120016:19:05(cdslmd)21400219002192016:19:05(cdslmd)22650228002281016:19:05(cdslmd)24015240252410016:19:05(cdslmd)2420525025116:19:05(cdslmd)2600027427616:19:05(cdslmd)27928330016:19:05(cdslmd)30531231416:19:05(cdslmd)3163183211016:19:05(cdslmd)32140321503219016:19:05(cdslmd)322325003250116:19:05(cdslmd)32502325103255016:19:05(cdslmd)32600326103262016:19:05(cdslmd)32630326403276016:19:05(cdslmd)330103330133416:19:05(cdslmd)336345003451016:19:05(cdslmd)36537037116:19:05(cdslmd)371003734002016:19:05(cdslmd)40030400404050016:19:05(cdslmd)41000500005001016:19:05(cdslmd)501501105020016:19:05(cdslmd)51022510235106016:19:05(cdslmd)510705117055016:19:05(cdslmd)570613006140016:19:05(cdslmd)71110711207113016:19:05(cdslmd)92094094516:19:05(cdslmd)95096096316:19:05(cdslmd)96496596616:19:05(cdslmd)97297499116:19:05(cdslmd)994995ABIT16:19:05(cdslmd)ALL_EBDAMD_MACHANALOG_WORKBENCH16:19:05(cdslmd)AWB_BEHAVIORAWB_BatchAWB_DIST_SIM16:19:05(cdslmd)AWB_MAGAZINEAWB_MAGNETICSAWB_MIX16:19:05(cdslmd)AWB_PPLOTAWB_RESOLVE_OPTAWB_SIMULATOR16:19:05(cdslmd)AWB_SMOKEAWB_SPICEPLUSAWB_STATS16:19:05(cdslmd)Actel_FPGAAdvanced_Cell_PlacerAdvanced_Package_Designer16:19:05(cdslmd)Affirma_AMS_distrib_processingAffirma_NC_SimulatorAffirma_NC_VHDL_Desktop_Sim16:19:05(cdslmd)Affirma_RF_IC_packageAffirma_RF_SPW_model_linkAffirma_advanced_analysis_env16:19:05(cdslmd)Affirma_equivalence_checkerAffirma_sim_analysis_envAllegro_CAD_Interface16:19:05(cdslmd)Allegro_DesignerAllegro_PCB_InterfaceAltera_MAX16:19:05(cdslmd)Ambit_BuildGatesAmbit_libcompileArtist_Optimizer16:19:05(cdslmd)Artist_StatisticsAtmel_ATVBOGUS16:19:05(cdslmd)Base_Digital_Body_LibBase_Verilog_LibBlockMaster_Characterizer16:19:05(cdslmd)BlockMaster_OptimizerBoardQuest_TeamBuildGates_Extreme16:19:05(cdslmd)CELL3CELL3_AROCELL3_CROSSTALK16:19:05(cdslmd)CELL3_CTSCELL3_ECLCELL3_OPENDEV16:19:05(cdslmd)CELL3_OPENEXECELL3_PACELL3_PR16:19:05(cdslmd)CELL3_QPLACE_TIMINGCELL3_SCANCELL3_TIMING16:19:05(cdslmd)CELL3_WIDEWIRECP_Ele_ChecksCPtoolkit16:19:05(cdslmd)CWAVESCWB01CWB0316:19:05(cdslmd)CWB04CWB05CheckPlus16:19:05(cdslmd)Clock_Tree_GenerationCobra_SimulatorComposerCheckPlus_AdvRules16:19:05(cdslmd)ComposerCheckPlus_CheckerComposerCheckPlus_RuleDevComposer_EDIF300_Connectivity16:19:05(cdslmd)Composer_EDIF300_SchematicComposer_Spectre_Sim_SolutionConcICe_Option16:19:05(cdslmd)Corners_AnalysisDISCRETE_LIBDRAC2CORE16:19:05(cdslmd)DRAC2DRCDRAC2LVSDRAC3CORE16:19:05(cdslmd)DRAC3DRCDRAC3LVSDRACACCESS16:19:05(cdslmd)DRACDISTDRACERCDRACLPE16:19:05(cdslmd)DRACLVSDRACPG_EDRACPLOT16:19:05(cdslmd)DRACPREDRACSLAVEDatapath_Preview_Option16:19:05(cdslmd)Datapath_VHDLDatapath_VerilogDevice_Level_Placer16:19:05(cdslmd)Device_Level_RouterDistributed_Dracula_OptionEBD_edit16:19:05(cdslmd)EBD_floorplanEBD_powerEDIF_Netlist_Interface16:19:05(cdslmd)EDIF_Schematic_InterfaceEMCdisplayEMControl16:19:05(cdslmd)Envisia_GE_ultra_place_routeEnvisia_PKSEnvisia_RAC16:19:05(cdslmd)Envisia_UtilityEnvisia_LowPower_optionEnvisia_DataPath_option16:19:05(cdslmd)Envisia_SE_ultra_place_routeExtended_Digital_Body_LibExtended_Digital_Lib16:19:05(cdslmd)Extended_Verilog_LibFPGA_FlowsFPGA_OPTIMIZER16:19:05(cdslmd)FPGA_ToolsFUNCTION_LIBFramework16:19:05(cdslmd)GATEENSEMBLEGATEENSEMBLE_AROGATEENSEMBLE_CROSSTALK16:19:05(cdslmd)GATEENSEMBLE_CTSGATEENSEMBLE_CTS_LEGATEENSEMBLE_CTS_UL16:19:05(cdslmd)GATEENSEMBLE_ECLGATEENSEMBLE_LOWENDGATEENSEMBLE_OPENDEV16:19:05(cdslmd)GATEENSEMBLE_OPENEXEGATEENSEMBLE_PAGATEENSEMBLE_PR_LE16:19:05(cdslmd)GATEENSEMBLE_PR_ULGATEENSEMBLE_QPLACE_TIMINGGATEENSEMBLE_SCAN16:19:05(cdslmd)GATEENSEMBLE_TIMINGGATEENSEMBLE_TIMING_LEGATEENSEMBLE_TIMING_UL16:19:05(cdslmd)GATEENSEMBLE_UNLIMITEDGATEENSEMBLE_WIDEWIREGate_Ensemble_DSM16:19:05(cdslmd)Gate_Ensemble_DSM_CrosstalkGate_Ensemble_WARPHDL-DESKTOP16:19:05(cdslmd)IC_InspectorIC_autorouteIC_edit16:19:05(cdslmd)IC_hsrulesIDF_Bi_Directional_InterfaceLAS_Cell_Optimization16:19:05(cdslmd)LEAPFROG-BVLEAPFROG-CVLEAPFROG-SLAVE16:19:05(cdslmd)LEAPFROG-SVLEAPFROG-SYSLID1016:19:05(cdslmd)LID11LINEAR_LIBLSE16:19:05(cdslmd)MAG_LIBMIXAD_LIBModel_Check_Analysis16:19:05(cdslmd)NCSim_DesktopNCVLOG_CGOPTSNC_Verilog_Compiler16:19:05(cdslmd)NC_Verilog_Data_Prep_CompilerNC_Verilog_SimulatorNC_VHDL_Simulator16:19:05(cdslmd)NC-simulatorNihongoconceptOASIS_Simulation_Interface16:19:05(cdslmd)OpenModeler_SFIOpenModeler_SWIFTOpenSim16:19:05(cdslmd)OpenWavesPICDesignerPIC_Utilities16:19:05(cdslmd)PLDPWM_LIBPearl16:19:05(cdslmd)Pearl_CellPlacement_Based_SynthesisPrevail_Board_Designer16:19:05(cdslmd)Prevail_Correct_By_DesignPrevail_DesignerPreview_Synopsys_Interface16:19:05(cdslmd)QPlaceQuickturn_Model_ManagerRapidPART16:19:05(cdslmd)SWIFTSchematic_GeneratorSigNoiseCS16:19:05(cdslmd)SigNoiseEngineerSigNoiseExpertSigNoiseStdDigLib16:19:05(cdslmd)Signal_IntegritySiliconQuestSiliconQuest_CTGen_Option16:19:05(cdslmd)Silicon_EnsembleSilicon_Ensemble_CTSSilicon_Ensemble_DSM16:19:05(cdslmd)Silicon_Ensemble_DSM_CrosstalkSilicon_Ensemble_OpenDevSilicon_Ensemble_OpenExe16:19:05(cdslmd)Silicon_Ensemble_WARPSilicon_Synthesis_QPBSSimControl16:19:05(cdslmd)SimVisionSpectreBasicSpectreRF16:19:05(cdslmd)Spectre_BTAHVMOS_ModelsSpectre_BTASOI_ModelsSpectre_NorTel_Models16:19:05(cdslmd)Spectre_ST_ModelsSubstrate_Coupling_AnalysisSynlink_Interface16:19:05(cdslmd)UETULMdeltaULMecho16:19:05(cdslmd)ULMhotelULMindiaULMjuliette16:19:05(cdslmd)ULMmikeUniversal_SmartpathVERILOG-SLAVE16:19:05(cdslmd)VERILOG-XLVERITIMEVHDLLink16:19:05(cdslmd)VHDL_desktopVXL-ALPHAVXL-LMC-HW-IF16:19:05(cdslmd)VXL-SWITCH-RCVXL-TURBOVXL-VCW16:19:05(cdslmd)VXL-VETVXL-VLSVXL-VRA16:19:05(cdslmd)Vampire_HDRCVampire_HLVSVampire_MP16:19:05(cdslmd)Vampire_RCXVampire_UIVerif_Ckpit_Analysis_Env16:19:05(cdslmd)Verilog_XL_Turbo_NTVerilog_XL_DesktopVerilog_desktop16:19:05(cdslmd)Virtuoso_Schem_OptionVirtuoso_XLXilinx_FPGA16:19:05(cdslmd)a2dxfaae-signalscanaae-signalscan-transaction16:19:05(cdslmd)aae-transaction-exploreractomdaffirma-signalscan16:19:05(cdslmd)affirma-signalscan-controlaffirma-signalscan-proaffirma-signalscan-schmatic16:19:05(cdslmd)affirma-signalscan-sourceaffirma-signalscan-transactionaffirma-transaction-explorer16:19:05(cdslmd)allegro_dfaallegro_dfa_attallegro_non_partner16:19:05(cdslmd)allegro_symbolallegroprancearchiver16:19:05(cdslmd)aroutercaeviewscals_out16:19:05(cdslmd)catiacbds_incdxe_in16:19:05(cdslmd)compcomposecompose_autoplan16:19:05(cdslmd)compose_gcrcompose_scellscompose_tlmr16:19:05(cdslmd)compose_utilconceptconceptXPC16:19:05(cdslmd)cpecptecrefer16:19:05(cdslmd)cvtomddebugdfsverifault16:19:05(cdslmd)dracula_indxf2ae2v16:19:05(cdslmd)edif2gedexpgenfethman16:19:05(cdslmd)fetsetupflukefsim16:19:05(cdslmd)gbomged2edifglib16:19:05(cdslmd)glossgphysdlygscald16:19:05(cdslmd)gspareshp3070iges_electrical16:19:05(cdslmd)intrglossintrrouteintrsignoise16:19:05(cdslmd)ipc_inipc_outlwb16:19:05(cdslmd)mdinmdoutmdtoac16:19:05(cdslmd)mdtocvmultiwirepackager16:19:05(cdslmd)pcb_editorpcb_engineerpcb_interactive16:19:05(cdslmd)pcb_preppcb_reviewpcomp16:19:05(cdslmd)placementplotVersaptc_in16:19:05(cdslmd)ptc_outquanticoutredifnet16:19:05(cdslmd)rtsdrc_insdrc_out16:19:05(cdslmd)signoiseskillDevstream_in16:19:05(cdslmd)stream_outswapsx16:19:05(cdslmd)synSmartIFsynSmartLibsynTiOpt16:19:05(cdslmd)tsTSynVHDLtsTSynVLOGtsTestGen16:19:05(cdslmd)tsTestIntftunetw0116:19:05(cdslmd)tw02v2evc-signalscan16:19:05(cdslmd)vc-signalscan-transactionvc-transaction-explorerverifault16:19:05(cdslmd)vgenviablevisula_in16:19:05(cdslmd)vloglinkwedifschxilCds16:19:05(cdslmd)xilComposerFExilConceptFExilEdif16:19:05(cdslmd)TimingAnalysisRCExtractionDelayCal16:19:05(cdslmd)TrialRouteAmoebaPlaceDesignViewer16:19:05(cdslmd)RouteCeltICSignalIntegrity16:19:05(cdslmd)ClockSynPowerAnalysisSpecialRoute16:19:05(cdslmd)TimingBudgetPartitionOptimizerFirstEncounter16:19:05(cdslmd)FirstEncounterSOCFE_ClassicFE_Ultra16:19:05(cdslmd)SOC_EncounterEncounter_CEnvisia_SE_SI_place_route16:19:05(cdslmd)NanoRoute_UltraNano_EncounterMultithread_Route_Option16:19:05(cdslmd)Cierto_SPW_comm_library_fxp_ptCierto_HW_design_sys_2000Cierto_SPW_multimedia_kit16:19:05(cdslmd)Cierto_SPW_GSM_VECierto_SPW_IS136_VECierto_SPW_pcscdma_VE16:19:05(cdslmd)Cierto_signal_proc_wrksys_2000Cierto_SPW_comm_lib_flt_ptSPW_Smart_Antenna_Library16:19:05(cdslmd)Cierto_Wireless_LAN_LibraryCierto_SPW_CDMA_LibraryCierto_SPW_model_manager16:19:05(cdslmd)16:19:05(cdslmd)AllFEATURElinesforthisvendorbehavelikeINCREMENTlines16:19:05(cdslmd)
3、上图已经说明license也是正确的，然后输入icfb&就可以顺利地满意地打开IC5141了。
4、下图是IC5141的新特性，不需要了解的话就可以关闭，其实每个cadence打开时都会跳出这样的界面，都可以关闭掉。
5、下图是开始建立一个新库的界面。和IC610是有点差别的。
6、下面就可以任意的画你的逻辑图了，记住前提是你必须加载你自己所需要的工艺库，不过这里加载库的确比IC610方便多了。
